1. Field of the Invention
The invention relates generally to junction capacitance within semiconductor structures. More particularly, the invention relates to junction capacitance reduction within semiconductor structures.
2. Description of the Related Art
Semiconductor structures and semiconductor devices often include semiconductor junctions that are formed between semiconductor regions of different polarity. Semiconductor junctions are an integral part of operation of certain types of semiconductor devices. For example, bipolar transistors and semiconductor diodes are predicated upon the operation of semiconductor junctions.
In other semiconductor structures, semiconductor junctions do not serve an operational purpose within semiconductor devices, but rather the semiconductor junctions result from a requirement that a first semiconductor region of a first polarity of necessity be formed within a second semiconductor region of a second polarity different from the first polarity. Examples of these types of semiconductor junctions are field effect transistor source/drain regions to doped well semiconductor junctions at locations remote from a channel region. Field effect transistor source/drain regions are typically of a polarity different from the polarity of a doped well within which they are formed and located.
The foregoing non-operational semiconductor junctions often possess undesirable characteristics that may compromise performance of a semiconductor structure or a semiconductor circuit within which they are formed. For example, a field effect transistor source/drain region to doped well semiconductor junction may in particular yield a semiconductor junction capacitance that otherwise compromises performance of the semiconductor circuit within which the field effect transistor is used. Such compromised performance may be in the form of an undesirable semiconductor junction capacitance contribution to a resistive-capacitive time delay within the semiconductor circuit.
Various novel semiconductor structures, and methods for fabrication thereof, that may be used for enhancing performance within semiconductor devices and circuits are known in the semiconductor fabrication art.
For example, Doyle et al., in U.S. Pat. No. 6,228,694, teaches a method for increasing charge carrier mobility within a metal oxide semiconductor (MOS) transistor by use of strategically located regions of locally enhanced stress. Within this particular prior art method, the regions of locally enhanced stress are formed incident to thermal annealing of a semiconductor substrate that was implanted with an inert material, to provide inert material voids within the semiconductor substrate.
In addition, Christiansen et al., in U.S. Pat. No. 6,855,649, teaches an ion implantation and thermal annealing method for forming a relaxed silicon-germanium alloy layer upon a silicon-on-insulator (SOI) substrate. This particular prior art method uses a helium ion implantation to provide platelets (and in particular not voids) beneath a silicon-germanium alloy layer to silicon layer interface within the silicon-on-insulator (SOI) substrate.
Further Akutsu, in U.S. Pub. No. 2005/0212087, teaches a particular bipolar transistor structure with a reduced collector-to-base capacitance. This particular prior art structure achieves the reduced collector-to-base capacitance by using laterally adjacent a collector pedestal located therein a low capacitance region comprising a void located within a dielectric layer.
Finally, Anderson et al., in U.S. Pat. No. 7,012,316, teaches an integrated circuit isolation structure that may be fabricated with enhanced efficiency. The integrated circuit isolation structure comprises: (1) a lower lying bubble implanted semiconductor region; and (2) an upper lying electrically insulating cap region.
Semiconductor structure dimensions and semiconductor device dimensions are certain to continue to decrease. As a result thereof, undesirable junction capacitance effects within certain semiconductor structures and certain semiconductor devices may become pronounced. Desirable are semiconductor structures, semiconductor devices and methods for fabricating the semiconductor structures and semiconductor devices that provide for reduced semiconductor junction capacitance.